鈮?/div>
1碌A at V
OL
, V
OH
September 1997
Features
鈥?Fully Static Operation
鈥?Buffered Inputs
鈥?Common Reset
鈥?Negative-Edge Clocking
鈥?Typical f
MAX
= 60 MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
[ /Title
(CD74
HC393
,
CD74
HCT39
3)
/Sub-
ject
(High
Speed
CMOS
Description
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master-
slave 铿俰p-铿俹ps. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER
CD74HC393E
CD74HCT393E
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
PACKAGE
14 Ld PDIP
14 Ld PDIP
PKG.
NO.
E14.3
E14.3
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP 1
1MR 2
1Q0 3
1Q1 4
1Q2 5
1Q3 6
GND 7
14 V
CC
13 2CP
12 2MR
11 2Q0
10 2Q1
9 2Q2
8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1997
File Number
1653.1
1